1. Field of the Invention
The invention relates to the field of semiconductor memory, and in particular, to a structure and method for providing non-volatile data storage in high-speed memory.
2. Related Art
Random access memory (RAM) is memory used in electronic device applications that provides direct access to stored data. The two main types of RAM are dynamic random access memory (DRAM) and static random access memory (SRAM). A schematic circuit diagram of a DRAM cell 100A is depicted in FIG. 1A. DRAM cell 100A includes a storage capacitor 111 and an access transistor 112. Access transistor 112 is connected between a bit line 113 and storage capacitor 111, and the gate of access transistor 112 is connected to a word line 114. To write a data value into a storage node 115 at a junction between storage capacitor 111 and access transistor 112, bit line 113 is set to the appropriate data level, and word line 114 is set to a logic HIGH level. The data level on bit line 113 charges or discharges storage capacitor 111, and word line 114 is then set to a logic LOW level, thereby isolating and storing the desired value at storage node 115.
To read the stored value from storage node 115, word line 114 is set to a logic HIGH level, and a sense amplifier (not shown for clarity) is used to read out the stored value by sensing the voltage on bit line 113. The simplicity and layout efficiency of DRAM cell 100A beneficially enables the implementation of low cost, high density DRAM memory arrays. However, a read operation to DRAM cell 100A destroys the data value stored at storage node 115, thereby necessitating a refresh operation to ensure that the data survives the read operation. In fact, DRAM cell 100A requires frequent refreshing due to charge leakage from storage capacitor 111. The overall speed of a memory array that incorporates DRAM cell 100A is partially limited by this dynamic refreshing that is required to maintain the stored data (e.g., >10 ns cell access time).
Therefore, high performance electronic devices that require high speed memory typically use SRAM arrays. FIG. 1B shows a schematic circuit diagram of a conventional SRAM cell 100B. SRAM cell 100B includes p-channel transistors 121 and 122, and n-channel transistors 131, 132, 133, and 134. Transistors 121 and 131 are connected in series between an upper supply voltage VDD and a lower supply voltage VSS (the reference or “ground” potential), and transistors 122 and 132 are connected in series between upper supply voltage VDD and VSS. The gates of transistors 121 and 131 are connected to the junction between transistors 122 and 132, and the gates of transistors 122 and 132 are connected to the junction between transistors 121 and 131. Transistors 121, 122, 131, and 132 therefore form a pair of cross-coupled inverters. Transistor 133 is connected between a bit line 141 and a storage node 161 at the junction between transistors 121 and 131, and transistor 134 is connected between a complementary bit line 142 and a complementary storage node 162 at the junction between transistors 122 and 132. The gates of transistors 133 and 134 are connected to a word line 150.
The cross-coupled inverters formed by transistors 121, 122, 131, and 132 act as a latch to store a data value at storage node 161 and a complement of the data value at storage node 162. To write a value into SRAM cell 100B, bit line 141 is set to the desired data level (i.e., voltage VBL) and bit line 142 is set to the complement of that data level (i.e., voltage/VBL). Word line 150 is then set to a logic HIGH level to turn on transistors 133 and 134 to allow the data on bit lines 141 and 142 to be latched into cross-coupled inverters formed by transistors 121, 122, 131, and 132. Word line 150 is then set back to a logic LOW level to turn off transistors 133 and 134, thereby isolating the latched data at storage nodes 161 and 162.
To perform a read operation, bit lines 141 and 142 are both driven to a logic HIGH level, after which word line 150 is set to a logic HIGH level to turn on transistors 133 and 134. Whichever of storage nodes 161 and 162 is storing a logic LOW value pulls down the associated one of bit lines 141 and 142, and this voltage change between bit lines 141 and 142 is detected by a differential sense amplifier (not shown) to determine the stored data value within SRAM cell 100B.
SRAM cell 100B is operationally faster (˜1 ns access time) than DRAM cell 100A, due to the transistors 131 and 132 which actively pull down the voltage on their respective bit line 141 or 142 when the voltage at their respective storage node 161 or 162 is at a logic LOW value. However, the larger number of transistors used in SRAM cell 100B (six transistors versus only one transistor in DRAM cell 100A) means that SRAM cell 100B consumes significantly more chip area than DRAM cell 100A, thereby undesirably increasing the cost of memory arrays that incorporate SRAM cells 100B. Furthermore, a problem common to both DRAM cell 100A and SRAM cell 100B is that both types of memory cells lose stored data when power is removed from the cells (i.e. when the supply voltage VDD goes to zero volts).
Flash semiconductor memory arrays commonly use a single floating gate transistor for each memory cell, and therefore can achieve very small cell size. However, flash memories exhibit relatively long read and write times (e.g., >20 ns read time and >100 ns write time) and have limited cell endurance (e.g., 105 read/write cycles). Therefore, flash memories are generally not suitable for high-speed, embedded RAM applications.
Some conventional efforts to add non-volatile properties to SRAM cells involve adding a floating gate transistor(s) to the SRAM cell. The floating gate transistor is used only for the storage of data during power down periods, thereby avoiding the speed and life cycle issues associated with flash memory implementations. Unfortunately, the floating gate transistor increases the size of the SRAM cell as well as the fabrication process complexity, and therefore undesirably increases layout inefficiency and cost.
Accordingly, it is desirable to provide a space-efficient SRAM memory cell/array with non-volatile storage capability.